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Altera_Forum
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14 years ago

Stratix III FPGA: Problem using Asynchronous FIFOs

Hi, I’m using a Stratix III FPGA and I have made a design using two interconnected Asynchronous FIFOs and when I launch the Post-Place and route simulation (using Modelsim) it doesn’t work...
Altera_Forum's avatar
Altera_Forum
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14 years ago

data_in probably has a set-up or hold violation, which explains the different output data.

For the additional SDC constraints you'd probably better read the manuals on TimeQuest.

There is another possible pitfall, I remember my colleague telling me that a dcfifo of depth 4 doesn't work well, hence he always uses a minimum depth of 8, I do too.