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Altera_Forum
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14 years ago

Stratix III FPGA: Problem using Asynchronous FIFOs

Hi, I’m using a Stratix III FPGA and I have made a design using two interconnected Asynchronous FIFOs and when I launch the Post-Place and route simulation (using Modelsim) it doesn’t work...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I'm using I/O files to test my design.First of all, Output Data aren't the same than Input Data. When I check the internal signals I see some control signals work wrong. Write and Read signals assert before Full and Empty ones (you can see it in the attached figure).

How are set_input_delay and set_output_delay used? What do you mean with set_clock_groups?