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Occasional Contributorhow to reduce clock skew between synchronous clock
I am working on Agilex 7 FPGA with quartus 25.3 software. In my project, there is 2 synchronous clocks that fast_clock is 416M and slow_clock is 208M. the clock scheme is
ref_clk_100m -> IOPLL -> 416M -> clk_ctrl_div_ip -> 416M/208M. And there is data transfer between clk_fast and clk_slow.
after compiling the whole design, I found there is large timing violation in the path that from clk_fast to clk_slow by timing report.
from the clk_fast-clk_slow timing path, the clock skew has -700ps
from clk_fast-clk_fast or clk_slow-clk_slow timing path, the clock skew is -5ps that is expected.
so how to reduce clock skew between synchronous clock? and could you provide more suggestions about how to implement data transfer clk_2x to clk_1x?
7 Replies
sstrellSuper Contributor
You should generate the slower clock from the same PLL. Putting a divider after the source clock and then transferring between the two clock domains going to cause issues as you are seeing.
You may also need to use multicycle timing exceptions to make sure the correct edges are used for the data transfers, but use the same source (PLL) first.
zjjthank you for replay! I will try！ and I have following 2 problems：
- clk_ctrl ip offers div1 and div2 port, actually clk_fast and clk_slow from the same clk_ctrl ip. quartus tool shall balance the clock tree between clk_fast and clk_slow ?
- the eth hard ip is used in my project! the eth hard ip offer 416M clk from the internal pll in the eth phy. my user design logic need use 208M clock and it is in the same clock group with eth_hard_ip_416M. now how can generate div2 clk? as I mentioned earlier, I use the clkctrl ip to generate div1 and div2 clk.
- sstrell
You should be setting this up in the IOPLL IP, not clk_ctrl. The clock control block is useful for putting clocks on particular clock resources, but everything starts with your PLL setup.
- zjj
okay, than you! can I use the eth_phy_pll_out_416M feed the freclk pin of IOPLL? if not, how can I generate div2 clk(208M) that is sync to eth_phy_pll_out_416M ?
cblixt1The example design available here might be useful: https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-7/i-series/ptp/agx7i-ptp-mcqos-25g/agx7i-ptp-mcqos-25g/
In it, you will find that the 415 MHz coming from the Ethernet Subsystem IP is used as a reference to an IOPLL generating 230 MHz.
Or try https://www.rocketboards.org/foswiki/Projects/AgilexSoCETileDesignExampleFor25GbeWithIEEE1588PTP, it might be closer to what you are doing.
- RichardT_altera
Any update regarding this case?
Let me know if further assistance is needed or if the solution worked for you.
Regards,
Richard Tan
