how to reduce clock skew between synchronous clock

I am working on Agilex 7 FPGA with quartus 25.3 software.  In my project, there is  2 synchronous clocks that fast_clock is 416M and  slow_clock is 208M.  the clock scheme is

ref_clk_100m -> IOPLL -> 416M -> clk_ctrl_div_ip -> 416M/208M.  And there is data transfer between clk_fast and clk_slow.

after compiling the whole design,  I found there is large timing violation in the path that from clk_fast to clk_slow  by timing report. 

from the clk_fast-clk_slow timing  path, the clock skew has -700ps

from clk_fast-clk_fast or clk_slow-clk_slow timing path, the clock skew is -5ps that is expected.

so how to reduce clock skew between synchronous clock? and could you provide more suggestions about how to implement data transfer clk_2x to clk_1x?