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zjj's avatar
zjj
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1 month ago

how to reduce clock skew between synchronous clock

I am working on Agilex 7 FPGA with quartus 25.3 software.  In my project, there is  2 synchronous clocks that fast_clock is 416M and  slow_clock is 208M.  the clock scheme is ref_clk_100m -> IOPLL -...
Timing
sstrell's avatar
sstrell
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1 month ago

You should generate the slower clock from the same PLL.  Putting a divider after the source clock and then transferring between the two clock domains going to cause issues as you are seeing.

You may also need to use multicycle timing exceptions to make sure the correct edges are used for the data transfers, but use the same source (PLL) first.

zjj's avatar
zjj
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1 month ago

thank you for replay! I will try！  and I have following 2 problems：

  1. clk_ctrl ip offers div1 and div2 port, actually clk_fast and clk_slow from the same clk_ctrl ip. quartus tool shall balance the clock tree between clk_fast and clk_slow ?
  2.  the eth hard ip is used in my project!  the eth hard ip offer 416M clk from the internal pll in the eth phy.  my user design logic need use 208M clock and it is in the same clock group with eth_hard_ip_416M. now how can generate div2 clk?  as I mentioned earlier, I use the clkctrl ip to generate div1 and div2 clk.