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zjj's avatar
zjj
Icon for New Contributor rankNew Contributor
17 hours ago

how to reduce clock skew between synchronous clock

I am working on Agilex 7 FPGA with quartus 25.3 software.  In my project, there is  2 synchronous clocks that fast_clock is 416M and  slow_clock is 208M.  the clock scheme is ref_clk_100m -> IOPLL -...
Timing
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 hours ago

You should generate the slower clock from the same PLL.  Putting a divider after the source clock and then transferring between the two clock domains going to cause issues as you are seeing.

You may also need to use multicycle timing exceptions to make sure the correct edges are used for the data transfers, but use the same source (PLL) first.