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zjj's avatar
zjj
Icon for Occasional Contributor rankOccasional Contributor
6 months ago

how to reduce clock skew between synchronous clock

I am working on Agilex 7 FPGA with quartus 25.3 software.  In my project, there is  2 synchronous clocks that fast_clock is 416M and  slow_clock is 208M.  the clock scheme is ref_clk_100m -> IOPLL -...
Timing
zjj's avatar
zjj
Icon for Occasional Contributor rankOccasional Contributor
6 months ago

okay, than you!  can I use the eth_phy_pll_out_416M  feed the  freclk pin  of IOPLL? if not, how can I generate div2 clk(208M) that is sync to  eth_phy_pll_out_416M ?

cblixt1's avatar
cblixt1
Icon for Occasional Contributor rankOccasional Contributor
6 months ago

The example design available here might be useful: https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-7/i-series/ptp/agx7i-ptp-mcqos-25g/agx7i-ptp-mcqos-25g/

In it, you will find that the 415 MHz coming from the Ethernet Subsystem IP is used as a reference to an IOPLL generating 230 MHz.

Or try https://www.rocketboards.org/foswiki/Projects/AgilexSoCETileDesignExampleFor25GbeWithIEEE1588PTP, it might be closer to what you are doing.