New Contributor
New Contributorokay, than you! can I use the eth_phy_pll_out_416M feed the freclk pin of IOPLL? if not, how can I generate div2 clk(208M) that is sync to eth_phy_pll_out_416M ?
New ContributorThe example design available here might be useful: https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-7/i-series/ptp/agx7i-ptp-mcqos-25g/agx7i-ptp-mcqos-25g/
In it, you will find that the 415 MHz coming from the Ethernet Subsystem IP is used as a reference to an IOPLL generating 230 MHz.
Or try https://www.rocketboards.org/foswiki/Projects/AgilexSoCETileDesignExampleFor25GbeWithIEEE1588PTP, it might be closer to what you are doing.
