New Contributor
Super ContributorYou should be setting this up in the IOPLL IP, not clk_ctrl. The clock control block is useful for putting clocks on particular clock resources, but everything starts with your PLL setup.
New Contributorokay, than you! can I use the eth_phy_pll_out_416M feed the freclk pin of IOPLL? if not, how can I generate div2 clk(208M) that is sync to eth_phy_pll_out_416M ?
New ContributorThe example design available here might be useful: https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-7/i-series/ptp/agx7i-ptp-mcqos-25g/agx7i-ptp-mcqos-25g/
In it, you will find that the 415 MHz coming from the Ethernet Subsystem IP is used as a reference to an IOPLL generating 230 MHz.
Or try https://www.rocketboards.org/foswiki/Projects/AgilexSoCETileDesignExampleFor25GbeWithIEEE1588PTP, it might be closer to what you are doing.
Super ContributorI am not familiar with the Ethernet hard IP. Which specific Ethernet IP are you using?
Have you tried generating an example design using your configuration settings and checking whether the example design includes an IOPLL IP that you can use as a reference?
Regards,
Richard Tan
