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Altera_Forum
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14 years ago

Stratix III FPGA: Problem using Asynchronous FIFOs

Hi, I’m using a Stratix III FPGA and I have made a design using two interconnected Asynchronous FIFOs and when I launch the Post-Place and route simulation (using Modelsim) it doesn’t work...
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Altera_Forum
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14 years ago

The frequencies I want to reach are: 200 MHz (CLK) and 280 MHz (CLK2). Fmax from Timequest are: 359.07 MHz (CLK) and 429.74 MHz (CLK2). I use a SDC file in Quartus where I set the time constrains: 4 ns for CLK and 3 ns for CLK2.

create_clock -period 4 -name clk [get_ports clk]

create_clock -period 3 -name clk2 [get_ports clk2]

derive_clock_uncertainty