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Altera_Forum
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14 years ago

Stratix III FPGA: Problem using Asynchronous FIFOs

Hi, I’m using a Stratix III FPGA and I have made a design using two interconnected Asynchronous FIFOs and when I launch the Post-Place and route simulation (using Modelsim) it doesn’t work...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I got setup errors in both clocks, but when I've removed the set_output_delay commands they have disappeared. Why does it happen?

I have got this frequencies: 224.52 MHz (CLK) and 378.36 MHz (CLK2). They seem too low for a design made from two FIFOs. What is the maximum frequency for the DCFIFO?

I generate the clocks using a testbench, have I to treat them as virtual clocks when I use the set_input_delay and set_output_delay commands?