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Altera_Forum
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14 years ago

Stratix III FPGA: Problem using Asynchronous FIFOs

Hi, I’m using a Stratix III FPGA and I have made a design using two interconnected Asynchronous FIFOs and when I launch the Post-Place and route simulation (using Modelsim) it doesn’t work...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I change the depth of the FIFOs to 8 words and the design works fine with Fast simulation and 0 ºC, but it doesn't work fine with Slow simulation and 85 ºC.