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I got setup errors in both clocks, but when I've removed the set_output_delay commands they have disappeared. Why does it happen?
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Because it could not meet the requested output timing, i.e. it could not guarantee proper setup times for the external devices.
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I have got this frequencies: 224.52 MHz (CLK) and 378.36 MHz (CLK2). They seem too low for a design made from two FIFOs. What is the maximum frequency for the DCFIFO?
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CLK has to deal with input signals, so it will have to factor in the input delays. Clk2 only deals with internal signals (as the output has a false path). Hence the difference bewteen the 2 clocks.
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I generate the clocks using a testbench, have I to treat them as virtual clocks when I use the set_input_delay and set_output_delay commands?
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No they are real clocks, they just happen to be generated by a testbench.
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