Stratix III FPGA: Problem using Asynchronous FIFOs

I've written a SDC file, I've compiled the design and it doesn't meet the timing constraints. I set the input and the output delays to zero. Have I written well the file?

# *******************************************************

# Created Clocks

# *******************************************************

create_clock -name clk -period 5 [get_ports clk]

create_clock -name clk2 -period 3.5 [get_ports clk2]

derive_clock_uncertainty

# *******************************************************

# Created Generated Clocks

# *******************************************************

derive_pll_clocks

# *******************************************************

# Set Clock Groups

# *******************************************************

set_clock_groups -asynchronous -group {clk} -group {clk2}

# *******************************************************

# Set False Paths

# *******************************************************

set_false_path -from [get_ports rst]

# *******************************************************

# Input Delays

# *******************************************************

set_input_delay -clock clk -max 0.0 [get_ports data_in[*]]

set_input_delay -clock clk -min 0.0 [get_ports data_in[*]]

set_input_delay -clock clk -max 0.0 [get_ports full_in]

set_input_delay -clock clk -min 0.0 [get_ports full_in]

set_input_delay -clock clk -max 0.0 [get_ports empty_in]

set_input_delay -clock clk -min 0.0 [get_ports empty_in]

# *******************************************************

# Output Delays

# *******************************************************

set_output_delay -clock clk -max 0.0 [get_ports wr[0]]

set_output_delay -clock clk -min 0.0 [get_ports wr[0]]

set_output_delay -clock clk2 -max 0.0 [get_ports wr[1]]

set_output_delay -clock clk2 -min 0.0 [get_ports wr[1]]

set_output_delay -clock clk2 -max 0.0 [get_ports rd[0]]

set_output_delay -clock clk2 -min 0.0 [get_ports rd[0]]

set_output_delay -clock clk -max 0.0 [get_ports rd[1]]

set_output_delay -clock clk -min 0.0 [get_ports rd[1]]

set_output_delay -clock clk -max 0.0 [get_ports full[0]]

set_output_delay -clock clk -min 0.0 [get_ports full[0]]

set_output_delay -clock clk2 -max 0.0 [get_ports full[1]]

set_output_delay -clock clk2 -min 0.0 [get_ports full[1]]

set_output_delay -clock clk2 -max 0.0 [get_ports empty[0]]

set_output_delay -clock clk2 -min 0.0 [get_ports empty[0]]

set_output_delay -clock clk -max 0.0 [get_ports empty[1]]

set_output_delay -clock clk -min 0.0 [get_ports empty[1]]

set_output_delay -clock clk2 -max 0.0 [get_ports data_mid[*]]

set_output_delay -clock clk2 -min 0.0 [get_ports data_mid[*]]

set_output_delay -clock clk -max 0.0 [get_ports data_out[*]]

set_output_delay -clock clk -min 0.0 [get_ports data_out[*]]