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Altera_Forum
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14 years ago

Stratix III FPGA: Problem using Asynchronous FIFOs

Hi, I’m using a Stratix III FPGA and I have made a design using two interconnected Asynchronous FIFOs and when I launch the Post-Place and route simulation (using Modelsim) it doesn’t work...
Altera_Forum's avatar
Altera_Forum
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14 years ago

how fast are we talking, and what fmax did Timequest tell you was the max speed?

The failure might be occuring accross the clock domain boundaries? IIRC, you have to tell timequest about these links yourself.