Stratix III FPGA: Problem using Asynchronous FIFOs

Looks quite OK to me.

You could do without the derive_pll_clocks, I believe you do not have a PLL in your design?

You can group pins together, so you have less typing to do: { wr[0] rd[0] full[0] ... } and the [get_ports ... ] is not necessary.

I usually set some small values for the input_delays, say -min 1.000 ns and -max 2.00 ns.

If it is a submodule I'm testing I don't care about the output delays and set them all as false-paths

What timing errors do you get?