Source-Synchoronous Interface: Edge Aligned SDR Clock constraint

Hi.

Iam designing using a Cypress FX3 device (CYUSB3014-BZXC) and a Cyclone IV FPGA(EP4CE115F29C8). The FPGA has a external 50 MHz oscillator. The design shouldrun @ 100 MHz. To do this I have an internal PLL to generate it.

TheFX3 device has a 32 bits source synchronous interface running @100MHz clockcoming from the FPGA. The FX3 device receive the data center-aligned.

As guidance for theport name I has the following ones:

moduleSLAVE_FIFO_STREAM_IN(
   input              CLOCK_50,      //input clp 50 Mhz
   inout            FX3_DQ,         //data bus
   output               FX3_faddr,       //output fifo address  
   output             FX3_slrd,        //output read select
   output             FX3_slwr,        //output write select
   input              FX3_flaga,      //full flag
   input              FX3_flagb,      //partial full flag
       input              FX3_flagc,      //empty flag
   input              FX3_flagd,     //empty partial flag
   output             FX3_sloe,      //output output enable select
   output             FX3_CLK,      //output clk 100 Mhz and 180 phase shift
   output             FX3_slcs,      //output chip select
   output             FX3_pktend, //output pkt end
   output               FX3_PMODE,
   output             FX3_RESET,
   output             FX3_PMODE_2 //used fordebugging
);

I already set thenext into my design:

1) Analtddio_out_component to shift the out clock 180° (Connected the datain_h(1'b0)and datain_l(1'b1) to make it)

2) I already set theoutput parallel interface as: "set_instance_assignment -nameFAST_OUTPUT_REGISTER ON"

3) My SDCconstraints are the next ones:

set_time_format-unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -nameCLOCK_50M -period 20.000 
create_generated_clock\
 -nameCLOCK_100M \
 -multiply_by 2\
 -source}] \
  }] 
#**************************************************************
# Create GeneratedClock
#**************************************************************
# Put a generatedclock on output clock port to be referenced by set_output_delay constraints. Note the -invert option, which says the clock is being inverted on theway out.  This is important
# since Quartusdoesn't recognize the DDR output with VCC/GND switched as inverting the clock
create_generated_clock-source }] -nameCLOCK_FX3  -invert
set_false_path -to
#Constrain the PLLautomatically
derive_pll_clocks-create_base_clocks
#**************************************************************
# Set ClockUncertainty
#**************************************************************
derive_clock_uncertainty
################################################################################
#Parameters
################################################################################
# Specify themaximum external clock delay to the FPGA
set FX3_CLKs_max 0
# Specify theminimum external clock delay to the FPGA
set FX3_CLKs_min 0
# Specify themaximum external clock delay to the external device
set FX3_CLKd_max 0
# Specify theminimum external clock delay to the external device
set FX3_CLKd_min 0
# Specify themaximum setup time of the external device
set FX3_tSU 2
# Specify theminimum setup time of the external device
set FX3_tH 0.5
# Specify themaximum board delay
set FX3_BD_max 0
# Specify theminimum board delay
set FX3_BD_min 0
# Specify themaximum clock-to-out of the external device
set FX3_tCO_max 9
# Specify theminimum clock-to-out of the external device
set FX3_tCO_min 2
################################################################################
#Output constraints
################################################################################       
set_output_delay-clock CLOCK_FX3 -max  
set_output_delay-clock CLOCK_FX3 -min   -add_delay
################################################################################
#Input constraints
################################################################################
set_input_delay-clock CLOCK_FX3 -max  
set_input_delay-clock CLOCK_FX3 -min                   

I have beenreviewing the Timequest guides provided in the AlteraWiki and the correspondingmanuals. But I cannot evacuate the next doubt:

As the design has aclock offset of 180° between the launch and the latch clock, (relative to theoutputs to the device) I do not know which is the right way to constraint this.I should use a set_multicycle_path command? The design has a synchonizer betweenthe register coming from the external device, but I do not know how tell thisto Timequest.

I attached a zippedfile for the design if this is easier to understand.

Thanks in advance.

Franco