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Altera_Forum
Honored Contributor
Honored ContributorSource-Synchoronous Interface: Edge Aligned SDR Clock constraint
Hi. Iam designing using a Cypress FX3 device (CYUSB3014-BZXC) and a Cyclone IV FPGA(EP4CE115F29C8). The FPGA has a external 50 MHz oscillator. The design shouldrun @ 100 MHz. To do this I have...
Altera_ForumHonored Contributor
Honored ContributorYou didn't answer my question. What is the timing requirement you need at the downstream device? Should it be 5 ns because of the 180 degree phase shift or does it need to be 15 ns (a cycle and a half)?
