Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Source-Synchoronous Interface: Edge Aligned SDR Clock constraint

Hi. Iam designing using a Cypress FX3 device (CYUSB3014-BZXC) and a Cyclone IV FPGA(EP4CE115F29C8). The FPGA has a external 50 MHz oscillator. The design shouldrun @ 100 MHz. To do this I have...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

I can see that just the failing lines are the lines conected to pins T7 and T8. Those are VREF pins. All the other are not. It this can be the issue? I heard about the higher capacitance for these pins. Maybe is this the problem? Can this be mitigated in some way?