Source-Synchoronous Interface: Edge Aligned SDR Clock constraint

But this is what you want, right? Or are you saying that the downstream device should have a cycle and a half for capture?

If it should be 5 ns, you can't use multicycle because that is just loosening the timing requirements (extending it to a cycle and a half = 15 ns).

If it needs to be 5 ns, you need to find other ways to make it work, such as launching the data earlier or latching the data later using phase shifts in the PLL. If you can do that, then you may need to use multicycle to compensate for it so that the timing analyzer chooses the correct edges for its analysis.

Have you looked at this training at all:

https://www.altera.com/support/training/course/ocss1000.html