Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorSource-Synchoronous Interface: Edge Aligned SDR Clock constraint
Hi. Iam designing using a Cypress FX3 device (CYUSB3014-BZXC) and a Cyclone IV FPGA(EP4CE115F29C8). The FPGA has a external 50 MHz oscillator. The design shouldrun @ 100 MHz. To do this I have...
Altera_ForumHonored Contributor
Honored ContributorOne note: you create PLL generated clocks and also call derive_pll_clocks. You should only do one or the other.
Other than that, this looks OK. The output generated clock is the latch clock and the -invert provides the 180 degree phase shift. You don't need multicycle here (that's only needed on an output in the edge aligned case). So what is the issue or problem you are having?
