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zjj's avatar
zjj
Icon for Occasional Contributor rankOccasional Contributor
2 months ago

dcfifo problem

In our project, we instantiate the parameterizable DCFIFO primitive provided by Altera. The design passes simulation verification without issues; however, mismatches occur between written and read data from the DCFIFO by signalTAP during board-level testing , which consequently causes driver loading failures.

fpga device：agilex7 with quartus pro25.3

dcfifo wr_clk: 450M

dcfifo rd_clk: 416M

the instantiate example:

is there better suggestion? 

Compilation
general

10 Replies

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    2 months ago

    Hi,

    Possible provide simulation waveform and signal tap waveform for taking a look? Or possible provide design for taking a look?

  • BCuze's avatar
    BCuze
    Icon for Occasional Contributor rankOccasional Contributor
    2 months ago

    I'm curious about how you test the discrepancy.
    From which clock does Signaltap run ? IMO, you should have two STPs, one on each clock. 

    Did you try pushing PRBS data and check what comes out ? Easier than STP IMO.

    • zjj's avatar
      zjj
      Icon for Occasional Contributor rankOccasional Contributor
      2 months ago

      yes!  one stp can contain two clock group! 

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    2 months ago

    This could also be a timing issue.  Is your design closing timing?

    • zjj's avatar
      zjj
      Icon for Occasional Contributor rankOccasional Contributor
      2 months ago

      yeah， timing is cleaning.  But I doesn't add afifo sdc.  is it may cause afifo output-data wrong ? 

      • BCuze's avatar
        BCuze
        Icon for Occasional Contributor rankOccasional Contributor
        2 months ago

        Even if it may seem counter-intuitive, an async fifo must be constrained ! (if only to ensure the skew on the Gray counters is low enough).

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    1 month ago

    Share this KDB Why do I see incorrect functionality in hardware for my DCFIFO and Mixed-Width DCFIFO Megafunction? | Altera Community - 343667 to you as well

    There's this previous bug and need the sdc constriants while disabling the embedded timing.

    However you not need to follow the workaround and just enable the parameter “Generate SDC file and disable embedded timing constraint” will do.

    For Arria 10 devices and onwards, the “Generate SDC file and disable embedded timing constraint” parameter under Timing Constraint section is checked by default. This allows you to bypass embedded timing constraints that uses set_false_path in the synchronization registers.