dcfifo problem

In our project, we instantiate the parameterizable DCFIFO primitive provided by Altera. The design passes simulation verification without issues; however, mismatches occur between written and read data from the DCFIFO by signalTAP during board-level testing , which consequently causes driver loading failures.

fpga device：agilex7 with quartus pro25.3

dcfifo wr_clk: 450M

dcfifo rd_clk: 416M

the instantiate example:

is there better suggestion?