Forum Discussion
zjj
Occasional Contributor
Occasional Contributordcfifo problem
In our project, we instantiate the parameterizable DCFIFO primitive provided by Altera. The design passes simulation verification without issues; however, mismatches occur between written and read da...
ShengN_altera
Super Contributor
Super ContributorHi,
Possible provide simulation waveform and signal tap waveform for taking a look? Or possible provide design for taking a look?
