Forum Discussion
zjj
Occasional Contributor
Occasional Contributordcfifo problem
In our project, we instantiate the parameterizable DCFIFO primitive provided by Altera. The design passes simulation verification without issues; however, mismatches occur between written and read da...
BCuzeOccasional Contributor
Occasional ContributorI'm curious about how you test the discrepancy.
From which clock does Signaltap run ? IMO, you should have two STPs, one on each clock.
Did you try pushing PRBS data and check what comes out ? Easier than STP IMO.
zjjOccasional Contributor
Occasional Contributoryes! one stp can contain two clock group!
