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zjj's avatar
zjj
Icon for Occasional Contributor rankOccasional Contributor
2 months ago

dcfifo problem

In our project, we instantiate the parameterizable DCFIFO primitive provided by Altera. The design passes simulation verification without issues; however, mismatches occur between written and read da...
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zjj's avatar
zjj
Icon for Occasional Contributor rankOccasional Contributor
2 months ago

yeah， timing is cleaning.  But I doesn't add afifo sdc.  is it may cause afifo output-data wrong ? 

BCuze's avatar
BCuze
Icon for Occasional Contributor rankOccasional Contributor
2 months ago

Even if it may seem counter-intuitive, an async fifo must be constrained ! (if only to ensure the skew on the Gray counters is low enough).