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zjj
Occasional Contributor
Occasional Contributordcfifo problem
In our project, we instantiate the parameterizable DCFIFO primitive provided by Altera. The design passes simulation verification without issues; however, mismatches occur between written and read da...
ShengN_altera
Super Contributor
Super ContributorShare this KDB Why do I see incorrect functionality in hardware for my DCFIFO and Mixed-Width DCFIFO Megafunction? | Altera Community - 343667 to you as well
There's this previous bug and need the sdc constriants while disabling the embedded timing.
However you not need to follow the workaround and just enable the parameter “Generate SDC file and disable embedded timing constraint” will do.
For Arria 10 devices and onwards, the “Generate SDC file and disable embedded timing constraint” parameter under Timing Constraint section is checked by default. This allows you to bypass embedded timing constraints that uses set_false_path in the synchronization registers.
