Forum Discussion
Occasional Contributordcfifo problem
Super ContributorThis could also be a timing issue. Is your design closing timing?
zjjyeah， timing is cleaning. But I doesn't add afifo sdc. is it may cause afifo output-data wrong ?
BCuzeEven if it may seem counter-intuitive, an async fifo must be constrained ! (if only to ensure the skew on the Gray counters is low enough).
ShengN_alteraIn fifo ip, there's Generate SDC File and disable embedded timing constraint options check below:
Related document: https://docs.altera.com/r/docs/683241/25.1.1/agilextm-7-embedded-memory-user-guide/dcfifo-timing-constraint-setting
Note: Altera recommends that you select this option for high frequency DCFIFO design to achieve timing closure.
- ShengN_altera
The related sdc enabled argument is this:
dcfifo_component.lpm_hint = "DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT=TRUE",
