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Altera_Forum
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7 years ago

Source-Synchoronous Interface: Edge Aligned SDR Clock constraint

Hi. Iam designing using a Cypress FX3 device (CYUSB3014-BZXC) and a Cyclone IV FPGA(EP4CE115F29C8). The FPGA has a external 50 MHz oscillator. The design shouldrun @ 100 MHz. To do this I have...
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Altera_Forum
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7 years ago

I already taken the webinar proposed. It is very interesting. I am using the DDIO OUTPUT register to drive the shifted clock : 

altddio_out_component	altddio_out_component_inst (
	.datain_h(1'b0),
	.datain_l(1'b1),
	.outclock(clk_100),
	.dataout(FX3_CLK) 
	);

I am following an example provided by Cypress doing this, but the parallel interface is not driven by another altddio component, instead is driven as a common tristate signal: 

assign FX3_DQ  = (slwr_streamIN_d1_) ? 32'dz : data_gen_stream_in;

I note now that the ddio register approach for SDR is the next one:

https://www.alteraforum.com/forum/attachment.php?attachmentid=15438

Maybe it is needed to use another altddio_out component to drive the FX3_DQ inout bus?