Source-Synchoronous Interface: Edge Aligned SDR Clock constraint

Hi Strell,

Thank you for you review. The issue that I have, is related to the clock relationship. As the internal register are clocked by the internal 100MHz and the external device is a clocked by a 180° 100 MHz offset, the design has a setup relationship of 5 ns instead or original 10 ns for the output and input register connected to the output/input pin.

I attached a figure for this violation.

https://alteraforum.com/forum/attachment.php?attachmentid=15430&stc=1

For instante, the FX3_flaga, FX3_flaga, FX3_flaga, FX3_flaga are signals cominf from the external device.

always @(posedge clk_100, negedge reset_)begin
    if(!reset_)begin 
        flaga_d <= 1'd0;
        flagb_d <= 1'd0;
        flagc_d <= 1'd0;
        flagd_d <= 1'd0;
    end else begin
        flaga_d <= FX3_flaga;
        flagb_d <= FX3_flagb;
        flagc_d <= FX3_flagc;
        flagd_d <= FX3_flagd;
    end    
end

The register connected to the FX3_flagx to flaga_x has a setup relationship of 5 ns.

Which is the right way to constraint this? a set_multicycle_path between them? or a set_false_path directive?