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Honored Contributor
Honored ContributorSource-Synchoronous Interface: Edge Aligned SDR Clock constraint
Hi. Iam designing using a Cypress FX3 device (CYUSB3014-BZXC) and a Cyclone IV FPGA(EP4CE115F29C8). The FPGA has a external 50 MHz oscillator. The design shouldrun @ 100 MHz. To do this I have...
Altera_ForumHonored Contributor
Honored ContributorOK, well if this is the case, then the problem is specific to those 4 paths failing timing. You do not want to add multicycle. All the other output data paths look fine. The sources for those 4 paths are different from the rest. Why? The path you highlight has a very large data delay internal to the device (over 2 ns). Are you forcing the source logic to a particular part of the device and then the data delay is incurred by having to get over to pin T7?
At this point, you need to use traditional timing closure techniques to fix these paths. The output interface itself does not seem to be the problem.
