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Altera_Forum
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8 years ago

Source-Synchoronous Interface: Edge Aligned SDR Clock constraint

Hi. Iam designing using a Cypress FX3 device (CYUSB3014-BZXC) and a Cyclone IV FPGA(EP4CE115F29C8). The FPGA has a external 50 MHz oscillator. The design shouldrun @ 100 MHz. To do this I have...
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Altera_Forum
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8 years ago

Ok, understand. Actually no. It is a 32 bits bus. Some lines (corresponding to lanes 31 & 29) are failing. But the entirely bus is assigned in th same way.

I am reviewing the report deeply. I can see some differences in the datapath regarding to the other lanes, but I think any was forced by me.

I attached the report file which I was researching. As you mentioned exist more than 2 nS of difference but it was not my intention to do it.