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Altera_Forum
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8 years ago

Source-Synchoronous Interface: Edge Aligned SDR Clock constraint

Hi. Iam designing using a Cypress FX3 device (CYUSB3014-BZXC) and a Cyclone IV FPGA(EP4CE115F29C8). The FPGA has a external 50 MHz oscillator. The design shouldrun @ 100 MHz. To do this I have...
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Altera_Forum
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8 years ago

I attached a timing diagram for this interface:

https://www.alteraforum.com/forum/attachment.php?attachmentid=15440

The clock is drived by the FPGA. The external device latchs the data in the clock rising edge. For this reason it is needed to make a 180° phase offset. I guess that this implies a 5 ns for the setup relationship. How it is possible to implement this interface due the delay timing?

Below is the picture for the paths failing, which are the output register connected to the data interface

https://www.alteraforum.com/forum/attachment.php?attachmentid=15441