New ContributorIssues debugging DDR3 controller using SignalTap on Quartus Prime Standard 23.1 with Arria V GZ FPGA
Hello,
I have a simple design where a state machine writes synthetic data to DDR using the Avalon bus of the DDR3 controller and reads it back after some time, processes it, and writes new data to DDR.
The state machine and all the logic is driven by the afi_clk PLL output of the IP.
The issue I am encountering is when trying to add all the AVL signals to signal tap, I can only see the ones driven by the logic and all the signals coming from the IP either pre-synthesis or post-fitting, are missing.
I have added the pragmas keep and preserve to avoid the compiler from optimizing them away or merging them. I have also registered the outputs and neither the original signal nor the registered ones show up on the SignalTap signal selector.
What is weirder is I can see the signals driven by the logic advancing in the state machine as expected (minus being clocked by the wrong clock since I cannot see the output clock of the IP).
Any help would be appreciated.
In this situation, it doesn't matter, it's the same signal no matter what.
Using pre-synth vs. post-fit comes more into play if you're trying to reduce recompile times (short ECO compilation with post-fit vs. full recomp with pre-synth even though in Standard edition, that isn't really a big thing either unless you are using incremental compilation).
Short answer for you: it doesn't really matter.
