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JuanEscobedo's avatar
JuanEscobedo
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8 months ago
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Issues debugging DDR3 controller using SignalTap on Quartus Prime Standard 23.1 with Arria V GZ FPGA

Hello, I have a simple design where a state machine writes synthetic data to DDR using the Avalon bus of the DDR3 controller and reads it back after some time, processes it, and writes new data to D...
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  • sstrell's avatar
    sstrell
    8 months ago

    In this situation, it doesn't matter, it's the same signal no matter what.

    Using pre-synth vs. post-fit comes more into play if you're trying to reduce recompile times (short ECO compilation with post-fit vs. full recomp with pre-synth even though in Standard edition, that isn't really a big thing either unless you are using incremental compilation).

    Short answer for you: it doesn't really matter.

JuanEscobedo's avatar
JuanEscobedo
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8 months ago

Afi_clk does appear, but only on pre-synthesis view in SignalTap

The signal is missing on post-fitting view

sstrell's avatar
sstrell
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8 months ago

So tap it as pre-synthesis for use as the acquisition clock.

  • JuanEscobedo's avatar
    JuanEscobedo
    Icon for New Contributor rankNew Contributor
    8 months ago

    What are the advantages/disadvantages of using pre synthesis vs post-fitting? Isn't the signal showing up in one but not the other a problem?

    • sstrell's avatar
      sstrell
      Icon for Super Contributor rankSuper Contributor
      8 months ago

      In this situation, it doesn't matter, it's the same signal no matter what.

      Using pre-synth vs. post-fit comes more into play if you're trying to reduce recompile times (short ECO compilation with post-fit vs. full recomp with pre-synth even though in Standard edition, that isn't really a big thing either unless you are using incremental compilation).

      Short answer for you: it doesn't really matter.

      • JuanEscobedo's avatar
        JuanEscobedo
        Icon for New Contributor rankNew Contributor
        8 months ago

        Hello,

        After changing the logic a bit and using the pre-synthesis signals to debug, I am able to get the behavior I expected:

        I have attached the version of the code that worked as reference. The main difference is my state machine was waiting on a registered version of the the ready and read data valid signals (part of previous attempts at troubleshooting). Changing the valid read condition to just the original read data valid signal seems to have solved the issue. Attaching my code for future reference.