Forum Discussion
New ContributorIssues debugging DDR3 controller using SignalTap on Quartus Prime Standard 23.1 with Arria V GZ FPGA
In this situation, it doesn't matter, it's the same signal no matter what.
Using pre-synth vs. post-fit comes more into play if you're trying to reduce recompile times (short ECO compilation with post-fit vs. full recomp with pre-synth even though in Standard edition, that isn't really a big thing either unless you are using incremental compilation).
Short answer for you: it doesn't really matter.
Super ContributorHave you tried searching on "afi_clk" instead of "avl_clk"? avl_clk does not appear in your tech map viewer screenshot even though you preserved it in your code.
JuanEscobedoAfi_clk does appear, but only on pre-synthesis view in SignalTap
The signal is missing on post-fitting view
- sstrell
So tap it as pre-synthesis for use as the acquisition clock.
- JuanEscobedo
What are the advantages/disadvantages of using pre synthesis vs post-fitting? Isn't the signal showing up in one but not the other a problem?
