JuanEscobedo
New Contributor
New ContributorIssues debugging DDR3 controller using SignalTap on Quartus Prime Standard 23.1 with Arria V GZ FPGA
Hello, I have a simple design where a state machine writes synthetic data to DDR using the Avalon bus of the DDR3 controller and reads it back after some time, processes it, and writes new data to D...
In this situation, it doesn't matter, it's the same signal no matter what.
Using pre-synth vs. post-fit comes more into play if you're trying to reduce recompile times (short ECO compilation with post-fit vs. full recomp with pre-synth even though in Standard edition, that isn't really a big thing either unless you are using incremental compilation).
Short answer for you: it doesn't really matter.
