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JuanEscobedo's avatar
JuanEscobedo
Icon for New Contributor rankNew Contributor
1 year ago
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Issues debugging DDR3 controller using SignalTap on Quartus Prime Standard 23.1 with Arria V GZ FPGA

Hello, I have a simple design where a state machine writes synthetic data to DDR using the Avalon bus of the DDR3 controller and reads it back after some time, processes it, and writes new data to D...
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  • sstrell's avatar
    sstrell
    1 year ago

    In this situation, it doesn't matter, it's the same signal no matter what.

    Using pre-synth vs. post-fit comes more into play if you're trying to reduce recompile times (short ECO compilation with post-fit vs. full recomp with pre-synth even though in Standard edition, that isn't really a big thing either unless you are using incremental compilation).

    Short answer for you: it doesn't really matter.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago

Can you clarify better what signals you can and cannot see? You say you "see the ones driven by the logic", but you can't see "the signals coming from the IP"? It's not clear what you mean by this. Like you can see the address bits (signals from logic to IP) but not readdata from the IP?

If you are talking about the memory signals that go out to the external memory, you can't tap those signals assuming you are using the hard controller.

JuanEscobedo's avatar
JuanEscobedo
Icon for New Contributor rankNew Contributor
1 year ago
Oh and to reiterate, I also cannot use the afi_clk output as the signaltap clock even though the state machine is driven by it and I see the state variable as well as the signals driven by the logic (addr, write data, write req, read req) toggle so it must be present and driving logic.