Forum Discussion
New ContributorIssues debugging DDR3 controller using SignalTap on Quartus Prime Standard 23.1 with Arria V GZ FPGA
In this situation, it doesn't matter, it's the same signal no matter what.
Using pre-synth vs. post-fit comes more into play if you're trying to reduce recompile times (short ECO compilation with post-fit vs. full recomp with pre-synth even though in Standard edition, that isn't really a big thing either unless you are using incremental compilation).
Short answer for you: it doesn't really matter.
Super ContributorI forgot that some IP call the waitrequest signal "ready" for some reason. The official name is waitrequest.
Does turning on "Include subentities" in the Node Finder do anything?
Check that the missing signals exist in the RTL Viewer and Technology Map Viewers. If they show up there but not in the Node Finder, something strange is going on.
JuanEscobedoHello!
A little bit of progress. I changed the state machine logic a little bit and now I can see the ready, data valid, and read data signals ( at least the registered version) so it seems it was indeed a problem of the logic was being optimized away. I have attached the latest version of my code for reference.
However, I still cannot add the afi_clk as the SignalTap instance. Using the RTL viewer I can confirm all 4 output signals from the controller are present:
And using the technology map viewer I can also confirm the missing signal (afi_clk) is present
Enabling "Include Sub entities" on SignalTap shows the ddr3 controller instance if trying to view the top level, but still, the clock signal is not found:
For completeness, here is a screenshot of the SignalTap instance running. You will see something is happening and in somewhat the right sequence, however, I am sampling using the system_clk which is 50MHz, and not the avl_clk which is 125MHz
