Forum Discussion
New ContributorIssues debugging DDR3 controller using SignalTap on Quartus Prime Standard 23.1 with Arria V GZ FPGA
In this situation, it doesn't matter, it's the same signal no matter what.
Using pre-synth vs. post-fit comes more into play if you're trying to reduce recompile times (short ECO compilation with post-fit vs. full recomp with pre-synth even though in Standard edition, that isn't really a big thing either unless you are using incremental compilation).
Short answer for you: it doesn't really matter.
New ContributorMy issue is the the avalon bus signals that are outputs of the IP. Namely, readdata, datavalid, and ready. They do not show up in signaltap neither presynthesis nor post fitting. Signals used as input to the controller which are driven by RTL show up fine.
Super Contributorready is not an Avalon signal. Do you mean waitrequest?
Can you show your design instantiation or design in Platform Designer and screenshots of what you're seeing when you try to tap the nodes in Signal Tap? If you're leaving signals unconnected, they may have been optimized away.
- JuanEscobedo
Hello,
I have attached the source RTL of my top level design and the top level RTL of the DDR3 controller generated by the wizard for your reference.
As you can see, avl_ready is indeed one of the ports of the avl interface for the DDR3 controller.
Below are the screenshots of the signals that show in post-fitting and pre-synthesis:
