module toplevel
(

	input 	wire 		system_clk,         
	
	output 	wire [15:0] mem_a,					
	output 	wire [2:0] 	mem_ba,					
	output 	wire 		mem_ck,					
	output 	wire 		mem_ck_n,				
	output 	wire 		mem_cke,					
	output 	wire 		mem_ras_n,				
	output 	wire 		mem_cas_n,				
	output 	wire 		mem_we_n,				
	output 	wire 		mem_reset_n,			
	output 	wire 		mem_cs_n,				
	inout 	wire [63:0] mem_dq,					
	inout 	wire [7:0] 	mem_dqs,				
	inout 	wire [7:0] 	mem_dqs_n,				
	output 	wire 		mem_odt,				
	input 	wire 		RZQ					


);


// State encoding
parameter IDLE    = 3'd0;
parameter WRITE   = 3'd1;
parameter WAIT    = 3'd2;
parameter READ    = 3'd3;
parameter WAITRD  = 3'd4;

// State machine registers
(* keep = "true", preserve = "true" *) reg [2:0] state;

// Avalon-MM Interface Signals
(* keep = "true", preserve = "true" *) reg  [25:0] avl_addr;
(* keep = "true", preserve = "true" *) reg         avl_read_req;
(* keep = "true", preserve = "true" *) wire [511:0] avl_rdata;
(* keep = "true", preserve = "true" *) reg         avl_write_req;
(* keep = "true", preserve = "true" *) reg  [511:0] avl_wdata;
(* keep = "true", preserve = "true" *) wire        avl_ready;
(* keep = "true", preserve = "true" *) reg         avl_burstbegin;
(* keep = "true", preserve = "true" *) reg  [7:0]   avl_size;
(* keep = "true", preserve = "true" *) reg  [63:0]  avl_be;
(* keep = "true", preserve = "true" *) wire        avl_rdata_valid;
(* keep = "true", preserve = "true" *) wire        avl_clk;

(* keep = "true", preserve = "true" *) reg [31:0] counter;
(* keep = "true", preserve = "true" *) wire rst;

// Registered DDR3 controller outputs
(* keep = "true", preserve = "true" *) reg [511:0] avl_rdata_reg;
(* keep = "true", preserve = "true" *) reg         avl_ready_reg;
(* keep = "true", preserve = "true" *) reg         avl_rdata_valid_reg;

always @(posedge system_clk)
    if (counter < 50000000)
        counter <= counter + 1;
		  
// Register controller outputs on avl_clk
always @(posedge avl_clk) begin
    avl_rdata_reg       <= avl_rdata;
    avl_ready_reg       <= avl_ready; 
    avl_rdata_valid_reg <= avl_rdata_valid;
end

assign rst = (counter == 50000000) ? 1'b1 : 1'b0;

// Initialization and FSM
always @(posedge avl_clk) begin 
    if (!rst) begin
        state           <= IDLE;
        avl_addr        <= 26'd0;
        avl_write_req   <= 1'b0;
        avl_read_req    <= 1'b0;
        avl_burstbegin  <= 1'b0;
        avl_size        <= 8'd0;
        avl_wdata       <= 512'd0;
        avl_be          <= 64'hFFFFFFFFFFFFFFFF;
    end else begin
        case (state)
            IDLE: begin
                avl_write_req   <= 1'b0;
                avl_read_req    <= 1'b0;
                avl_burstbegin  <= 1'b0;
                avl_size        <= 8'd0;

                if (avl_ready) begin
                    avl_write_req   <= 1'b1;
                    avl_burstbegin  <= 1'b1;
                    avl_size        <= 8'd1;
                    state           <= WRITE;
                end
            end

            WRITE: begin
                avl_write_req   <= 1'b0;
                avl_burstbegin  <= 1'b0;
                avl_size        <= 8'd0;
                state           <= WAIT;
            end

            WAIT: begin
                state           <= READ;
            end

            READ: begin
                if (avl_ready) begin
                    avl_read_req    <= 1'b1;
                    avl_burstbegin  <= 1'b1;
                    avl_size        <= 8'd1;
                    state           <= WAITRD;
                end else begin
                    avl_read_req    <= 1'b0;
                    avl_burstbegin  <= 1'b0;
                    avl_size        <= 8'd0;
                end
            end

            WAITRD: begin
                avl_read_req    <= 1'b0;
                avl_burstbegin  <= 1'b0;
                avl_size        <= 8'd0;
                avl_addr        <= avl_addr + 1;
                avl_wdata       <= avl_wdata + 1;
                state           <= IDLE;
            end

            default: state <= IDLE;
        endcase
    end
end

ddr3L_quarter u_ddr3L_quarter (
    // Clocks & Reset
    .pll_ref_clk               (system_clk),                // input
    .global_reset_n            (rst),             // input
    .soft_reset_n              (rst),               // input

    // AFI Outputs
    .afi_clk                   (avl_clk),                    // output
    .afi_half_clk              (),               // output
    .afi_reset_n               (),                // output
    .afi_reset_export_n        (),         // output

    // DDR3 Memory Interface
    .mem_a                     (mem_a),                      // output [15:0]
    .mem_ba                    (mem_ba),                     // output [2:0]
    .mem_ck                    (mem_ck),                     // output [0:0]
    .mem_ck_n                  (mem_ck_n),                   // output [0:0]
    .mem_cke                   (mem_cke),                    // output [0:0]
    .mem_cs_n                  (mem_cs_n),                   // output [0:0]
    .mem_ras_n                 (mem_ras_n),                  // output [0:0]
    .mem_cas_n                 (mem_cas_n),                  // output [0:0]
    .mem_we_n                  (mem_we_n),                   // output [0:0]
    .mem_reset_n               (mem_reset_n),                // output
    .mem_dq                    (mem_dq),                     // inout  [63:0]
    .mem_dqs                   (mem_dqs),                    // inout  [7:0]
    .mem_dqs_n                 (mem_dqs_n),                  // inout  [7:0]
    .mem_odt                   (mem_odt),                    // output [0:0]

    // Avalon Interface
    .avl_addr                  (avl_addr),                   // input  [25:0]
    .avl_read_req              (avl_read_req),               // input
    .avl_rdata                 (avl_rdata),                  // output [511:0]
    .avl_write_req             (avl_write_req),              // input
    .avl_wdata                 (avl_wdata),                  // input  [511:0]
    .avl_ready                 (avl_ready),                  // output
    .avl_burstbegin            (avl_burstbegin),             // input
    .avl_size                  (avl_size),                   // input  [7:0]
    .avl_be                    (avl_be),                     // input  [63:0]
    .avl_rdata_valid           (avl_rdata_valid),            // output

    // Status
    .local_init_done           (),            // output
    .local_cal_success         (),          // output
    .local_cal_fail            (),             // output

    // User Refresh
    //.local_refresh_req         (),          // input
    //.local_refresh_chip        (),         // input  [0:0]
    //.local_refresh_ack         (),          // output

    // OCT
    .oct_rzqin                 (RZQ),                  // input 

    // PLL Sharing
    .pll_mem_clk               (),                // output
    .pll_write_clk             (),              // output
    .pll_locked                (),                 // output
    .pll_write_clk_pre_phy_clk (),  // output
    .pll_addr_cmd_clk          (),           // output
    .pll_avl_clk               (),                // output
    .pll_config_clk            (),             // output
    .pll_hr_clk                (),                 // output
    .pll_p2c_read_clk          (),           // output
    .pll_c2p_write_clk         (),          // output

    // Sequencer Debug Interface
    .seq_debug_addr            (),             // input  [19:0]
    .seq_debug_read_req        (),         // input
    .seq_debug_rdata           (),            // output [31:0]
    .seq_debug_write_req       (),        // input
    .seq_debug_wdata           (),            // input  [31:0]
    .seq_debug_waitrequest     (),      // output
    .seq_debug_be              (),               // input  [3:0]
    .seq_debug_rdata_valid     ()       // output
);


endmodule