Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa

Wanted to give an update.

After I hit Generate Design Example with my specific IP patters as Gen3 x 8, 250 Mhz, DMA enabled, Simulation only, and I have applied these settings to the Intel Stratix 10 GX FPGA Development Kit DK-DEV-1SGX-H-A under Board settings, the design fails to generate the example.

The output from the IP editor window is in the attached file.

I've also kept the same settings to another board I have I bought from Terasic, the Apollo S10 SOM, which has a similar chipset

as the above but isn't listed under the Boards, so I click "None" and generate design, and it still fails to provide a simulation model.

Can anyone explain this or provide me with a simulation model, as long as it's Gen3x8, I don't mind ? Or tell me whats going wrong here?

All simulation options are correctly followed in the User Guide. Does anyone else have this issue ?

Hi,

I'd like to confirm with you which IP you're using. AVMM or AVMM+ for PCIe?

I'm following the user guide L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express and using Questa Intel FPGA Edition to simulate.

--AVMM+ PCIe only provides Gen3x16 512 bit 250 MHz, not selectable; DMA is the only example, not changeable

After I hit Generate Design Example with my specific IP patters as Gen3 x 8, 250 Mhz, DMA enabled, Simulation only

--AVMM PCIe can select to this setting, Gen 3x8 256 bit 250 MHz DMA

Regards,

Rong

It looks like the failure happens during example design generation.

Line 358 of the text file shows your project path has a space, please fix this first then regenerate example design.

As p.19 says, turn on the Simulation and Synthesis options, for DMA design please Enable Avalon-MM DMA.

Regards,

Rong

Open your generated example design and run "Analysis & Synthesis". After this is done, go to pcie_ed_tb/pcie_ed_tb/sim/mentor and do "vsim" etc described at page 21 in user guide.

Regards,

Rong

Complete "Analysis & Synthesis" before you do simulation.

I did the Analysis and Synthesis as recommended, and the design still does not compile.

The generated design does say it generated sucessfully.

Upon invoking vsim and running do msim_setup.tcl and ld_debug the last message says "Error loading design". Doesn't explain what file it can't locate or find. I've followed all instructions on p. 19-21 and still fails.

I was able to suppress other past errors as the paths to the design filed was over the 128 character limit on Windows, by

changing Windows environment variable LongPathsEnabled to "1".

[HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\FileSystem] LongPathsEnabled=1

Can you please confirm on your end by generating the design example for my device, 1SX280HU2F50E1VG, and using Questa it works?

Not sure why it's not loading the design?

I believe I found the issue, but I still need to fix this.

So I've done all steps above and as correctly done per the User Guide on p. 19-21. Again, it claims "Error loading design"

Opening Questa and changing directory to the testbench directy and under sim for mentor, I type in do msim_setup.tcl, it maps all my libraries to the files and modules of the testbench directory. I noticed there is apparently a Library Mapping Mismatch. The project window list various files that don't map to the location of the file in my project location on my host drive. But when I click Edit, it seems to find it. Double clicking it though says module isn't defined and couldn't load it. There needs to a be a 1-to-1 mapping of these files as listed in the Library window.

So the issue is the msim_setup.tcl needs to correctly map the location of my design files on my host drive. I'm not familir with .tcl files.

To assist in arriving at a solution,

This is the location of my design file

C:\intelFPGA_pro\23.3\pcie_s10_hip_avmm_bridge_0_example_design

and here is the simulation directory

C:\intelFPGA_pro\23.3\pcie_s10_hip_avmm_bridge_0_example_design\pcie_ed_tb\pcie_ed_tb\sim\mentor

I tried on linux using 1SX280HU2F50E2VG and Questa worked fine. The sim took a while to complete.

After synthesis, I went to pcie_ed_tb/pcie_ed_tb/sim/mentor, typed vsim there, then did "do msim_setup.tcl", "ld_debug" and "run -all" inside Questa.

If you check msim_setup.tcl, the QSYS_SIMDIR ./../ should point to the directory of pcie_ed_tb.v and common. I suggest you do the same thing with me. Go to pcie_ed_tb/pcie_ed_tb/sim/mentor and type vsim to start Questa there.

Regards,

Rong

Once you have project generated, continue doing synthesis & simulation.

Do not use "Clean Project". I found this function cleans several sim directories which cannot be recovered. Your library mapping issue probably because of this.

Regards,

Rong

Hi,

I've done everything you've told me, followed the directions in the user guide, and unfortunately it is not compiling or loading the design. Nothing I do works.

Can I please have this case elevated and have another support person and fresh eyes to evaluate the issue?

For reference, I have a Windows 11 computer and running designs on Questa Intel Starter Edition 2032.2. Generated design was used on Quartus Pro 23.3.

I believe you ran simulation on Linux.

I've tried now simulating the Gen3 x 16 lane IP core, per the instructions in the L-Tile and H-Tile Avalon MM + Intel FPGA IP for PCI Express User Guide on pp. 12-16. I've selected the right core (MM+) on the toolbar to generate my IP variant and selected the options as listed on p. 14 of the User Guide. My specific FPGA is 1SX280HU2F50E1VG

Sucessfully generated the design example. Open up Questa, change to this directory

C:\intelFPGA_pro\23.3\avmm_bridge_512_0_example_design\pcie_ed_tb\pcie_ed_tb\sim\mentor

I run

do msim_setup.tcl

Then I run

ld_debug

I have over 3500 warnings and finally "failed to load design."

I've attached the complete transcript run.

It does NOT work on a Windows 11 computer.

I am assuming this is a mapping error.