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RHobb
Occasional Contributor
Occasional ContributorSimulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa
I'm following the user guide L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express and using Questa Intel FPGA Edition to simulate. This is for Quartus Prime Design Suite 23.4. I followed the p...
Thanks for the sharing of your conclusion and findings.
You're right. The simulation of S10 PCIe AVMM example design has problem which reports "FAILURE: Simulation stopped due to Fatal error!". After checked, the same issue exists in Q25.1 Pro as well. This is a bug that we need to fix.
Regards,
Rong
RongY_altera
Contributor
ContributorOpen your generated example design and run "Analysis & Synthesis". After this is done, go to pcie_ed_tb/pcie_ed_tb/sim/mentor and do "vsim" etc described at page 21 in user guide.
Regards,
Rong
