Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa

Hi,

I've done everything you've told me, followed the directions in the user guide, and unfortunately it is not compiling or loading the design. Nothing I do works.

Can I please have this case elevated and have another support person and fresh eyes to evaluate the issue?

For reference, I have a Windows 11 computer and running designs on Questa Intel Starter Edition 2032.2. Generated design was used on Quartus Pro 23.3.

I believe you ran simulation on Linux.

I've tried now simulating the Gen3 x 16 lane IP core, per the instructions in the L-Tile and H-Tile Avalon MM + Intel FPGA IP for PCI Express User Guide on pp. 12-16. I've selected the right core (MM+) on the toolbar to generate my IP variant and selected the options as listed on p. 14 of the User Guide. My specific FPGA is 1SX280HU2F50E1VG

Sucessfully generated the design example. Open up Questa, change to this directory

C:\intelFPGA_pro\23.3\avmm_bridge_512_0_example_design\pcie_ed_tb\pcie_ed_tb\sim\mentor

I run

do msim_setup.tcl

Then I run

ld_debug

I have over 3500 warnings and finally "failed to load design."

I've attached the complete transcript run.

It does NOT work on a Windows 11 computer.

I am assuming this is a mapping error.