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RHobb's avatar
RHobb
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa

I'm following the user guide L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express and using Questa Intel FPGA Edition to simulate. This is for Quartus Prime Design Suite 23.4. I followed the p...
Pcie
  • RongY_altera's avatar
    RongY_altera
    1 year ago

    Thanks for the sharing of your conclusion and findings.


    You're right. The simulation of S10 PCIe AVMM example design has problem which reports "FAILURE: Simulation stopped due to Fatal error!". After checked, the same issue exists in Q25.1 Pro as well. This is a bug that we need to fix.


    Regards,

    Rong


RHobb's avatar
RHobb
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Wanted to give an update.

After I hit Generate Design Example with my specific IP patters as Gen3 x 8, 250 Mhz, DMA enabled, Simulation only, and I have applied these settings to the Intel Stratix 10 GX FPGA Development Kit DK-DEV-1SGX-H-A under Board settings, the design fails to generate the example.

The output from the IP editor window is in the attached file.

I've also kept the same settings to another board I have I bought from Terasic, the Apollo S10 SOM, which has a similar chipset

as the above but isn't listed under the Boards, so I click "None" and generate design, and it still fails to provide a simulation model.

Can anyone explain this or provide me with a simulation model, as long as it's Gen3x8, I don't mind ? Or tell me whats going wrong here?

All simulation options are correctly followed in the User Guide. Does anyone else have this issue ?