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RHobb's avatar
RHobb
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
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Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa

I'm following the user guide L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express and using Questa Intel FPGA Edition to simulate. This is for Quartus Prime Design Suite 23.4. I followed the p...
Pcie
  • RongY_altera's avatar
    RongY_altera
    1 year ago

    Thanks for the sharing of your conclusion and findings.


    You're right. The simulation of S10 PCIe AVMM example design has problem which reports "FAILURE: Simulation stopped due to Fatal error!". After checked, the same issue exists in Q25.1 Pro as well. This is a bug that we need to fix.


    Regards,

    Rong


RongY_altera's avatar
RongY_altera
Icon for Contributor rankContributor
1 year ago

I tried on linux using 1SX280HU2F50E2VG and Questa worked fine. The sim took a while to complete.


After synthesis, I went to pcie_ed_tb/pcie_ed_tb/sim/mentor, typed vsim there, then did "do msim_setup.tcl", "ld_debug" and "run -all" inside Questa.


If you check msim_setup.tcl, the QSYS_SIMDIR ./../ should point to the directory of pcie_ed_tb.v and common. I suggest you do the same thing with me. Go to pcie_ed_tb/pcie_ed_tb/sim/mentor and type vsim to start Questa there.



Regards,

Rong