Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa

I believe I found the issue, but I still need to fix this.

So I've done all steps above and as correctly done per the User Guide on p. 19-21. Again, it claims "Error loading design"

Opening Questa and changing directory to the testbench directy and under sim for mentor, I type in do msim_setup.tcl, it maps all my libraries to the files and modules of the testbench directory. I noticed there is apparently a Library Mapping Mismatch. The project window list various files that don't map to the location of the file in my project location on my host drive. But when I click Edit, it seems to find it. Double clicking it though says module isn't defined and couldn't load it. There needs to a be a 1-to-1 mapping of these files as listed in the Library window.

So the issue is the msim_setup.tcl needs to correctly map the location of my design files on my host drive. I'm not familir with .tcl files.

To assist in arriving at a solution,

This is the location of my design file

C:\intelFPGA_pro\23.3\pcie_s10_hip_avmm_bridge_0_example_design

and here is the simulation directory

C:\intelFPGA_pro\23.3\pcie_s10_hip_avmm_bridge_0_example_design\pcie_ed_tb\pcie_ed_tb\sim\mentor