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Occasional ContributorSimulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa
Thanks for the sharing of your conclusion and findings.
You're right. The simulation of S10 PCIe AVMM example design has problem which reports "FAILURE: Simulation stopped due to Fatal error!". After checked, the same issue exists in Q25.1 Pro as well. This is a bug that we need to fix.
Regards,
Rong
ContributorHi,
I'd like to confirm with you which IP you're using. AVMM or AVMM+ for PCIe?
I'm following the user guide L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express and using Questa Intel FPGA Edition to simulate.
--AVMM+ PCIe only provides Gen3x16 512 bit 250 MHz, not selectable; DMA is the only example, not changeable
After I hit Generate Design Example with my specific IP patters as Gen3 x 8, 250 Mhz, DMA enabled, Simulation only
--AVMM PCIe can select to this setting, Gen 3x8 256 bit 250 MHz DMA
Regards,
Rong
RHobbHi,
I'm using the L-tile and H-tile Avalon® Memorymapped Intel® FPGA IP for PCI Express
So I've set it to Gen3x8, 256 bit 250 MHz DMA
I've set all parameters according to the User Guide on p. 19, this is for Quartus Prime Suite 21.1
I previously included the error file, which stops at the error saying it can't
find aldec/altera_pcie_s10_64avmm_adapter/altera_pcie_s10_adapter.v
Then says failed to generate design example.
Despite the error, I try to simulate in Questa by changing the working directory to the design example, it won't load the design.
