Forum Discussion
Occasional ContributorSimulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa
Thanks for the sharing of your conclusion and findings.
You're right. The simulation of S10 PCIe AVMM example design has problem which reports "FAILURE: Simulation stopped due to Fatal error!". After checked, the same issue exists in Q25.1 Pro as well. This is a bug that we need to fix.
Regards,
Rong
ContributorIt looks like the failure happens during example design generation.
Line 358 of the text file shows your project path has a space, please fix this first then regenerate example design.
As p.19 says, turn on the Simulation and Synthesis options, for DMA design please Enable Avalon-MM DMA.
Regards,
Rong
Occasional ContributorI got rid of the spaces, and again tried compiling the design in Questa. It has output a new error message and stops.
# ** Error: (vlog-7) Failed to open design unit file "../../../../ip/pcie_ed/pcie_ed_DUT/altera_pcie_s10_hip_avmm_bridge_2223/sim/pcie_ed_DUT_altera_pcie_s10_hip_avmm_bridge_altera_xcvr_pcie_hip_native_s10_2223_bbreury.v" in read mode.
# No such file or directory. (errno = ENOENT)
Since Intel has now obsolete static design examples, is there a legacy model that you can upload that I can use to simulate? I believe the problem exists when I don't have a Intel FPGA Board, but the Terasic Apollo S10 SOM which means I have to put no board design but otherwise put my chipset in and have a dynamic configuration and thats the problem. Can you try and put my chipset in an try to dynamically generate a design example and simulate it with no errors? 1SX280HU2F50E1VG
