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RHobb's avatar
RHobb
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
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Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa

I'm following the user guide L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express and using Questa Intel FPGA Edition to simulate. This is for Quartus Prime Design Suite 23.4. I followed the p...
Pcie
  • RongY_altera's avatar
    RongY_altera
    1 year ago

    Thanks for the sharing of your conclusion and findings.


    You're right. The simulation of S10 PCIe AVMM example design has problem which reports "FAILURE: Simulation stopped due to Fatal error!". After checked, the same issue exists in Q25.1 Pro as well. This is a bug that we need to fix.


    Regards,

    Rong


RHobb's avatar
RHobb
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

I did the Analysis and Synthesis as recommended, and the design still does not compile.

The generated design does say it generated sucessfully.

Upon invoking vsim and running do msim_setup.tcl and ld_debug the last message says "Error loading design". Doesn't explain what file it can't locate or find. I've followed all instructions on p. 19-21 and still fails.

I was able to suppress other past errors as the paths to the design filed was over the 128 character limit on Windows, by

changing Windows environment variable LongPathsEnabled to "1".

[HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\FileSystem] LongPathsEnabled=1

Can you please confirm on your end by generating the design example for my device, 1SX280HU2F50E1VG, and using Questa it works?

Not sure why it's not loading the design?