Intel P-tile HIP clock not visible during timing analysis "all clock report"

Question

We are trying to run ptile pcie in end_point mode + user_logic, but during timing analysis "coreclkout_hip" the one generated by HIP ( hard pcie_ip core) and fed to user_logic , is not visible in the "all clocks report"

what would be the procedure to enable this?

In Gen 3 1x8 256 bit with 250 Mhz mode, Quartus is not able to automatically detect this "coreclkout_hip" and do the timing analysis of user_logic that's synchronous with respect to this clock

shengn_altera · Answer

Hi,May i know you generate the design example with pio?Thanks,Regards,Sheng

adithiya_r · Answer

Hi Sheng

We generate the intel Ptile ip with our custom logic instead of PIO, and these are the following ports, which are given below
rx/tx_pma_parllel_clk, ref_clk these are the only list getting visible, coreclkout_hip which is supposed to be 350 Mhz (gen4) or 250 Mhz(gen3) is not in the list
Requirement : To perform timing analysis with respect to coreclkouthip or the corresponding port in custom logic (user_clk)

shengn_altera · Answer

Hi,Please make sure the output clock coreclkout_hip being used internally like feeding to other logic. Make sure there's fanout or usage internally. May I know possible provide the design for taking a look?Thanks,Regards,Sheng

adithiya_r · Answer

It is directly connected to user_app, user_clk port. But not identified as clock by Quartus.

shengn_altera · Answer

Hi,Have you properly output the user logic? I'm adfraid it's being optimized away.Could you set Netlist Optimization Never Allowed to that user logic module?Thanks,Regards,Sheng