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Adithiya_R
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5 months ago

Intel P-tile HIP clock not visible during timing analysis "all clock report"

Hi Everyone, We are trying to run ptile pcie in end_point mode + user_logic, but during timing analysis "coreclkout_hip" the one generated by HIP ( hard pcie_ip core) and fed to user_logi...
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Adithiya_R's avatar
Adithiya_R
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5 months ago

Hi,

Yes, our user logic is unstable at 350 MHz.

To figure this out we need to enable the Timing analysis with respect to Coreclkout_hip

That clock is not seen in the timing analysis. How to enable that?