Forum Discussion
Adithiya_R
New Contributor
New ContributorIntel P-tile HIP clock not visible during timing analysis "all clock report"
Hi Everyone, We are trying to run ptile pcie in end_point mode + user_logic, but during timing analysis "coreclkout_hip" the one generated by HIP ( hard pcie_ip core) and fed to user_logi...
RongY_altera
Contributor
ContributorTesting a PCIe Gen4 1x8 350MHz PIO design in Q25.1 Pro, the coreclkout_hip can be seen at the pio side as below screenshot. You may find similar clock input for your user logic.
Another two 350MHz clocks from dut|dut|inst|Inst|maib_and_tile are from a pcie wrapper file already constrained in pcie sdc files.
Regards,
Rong
